Mastering Digital Vlsi, Asic And Verilog Interview Questions

Description
Do you want access to all the questions that are asked at the Big Tech Companies Do you want to feel supremely confident going into the interview process Do you want to ACE all the interviews and get the best possible offer(s)If your answer to any of these questions is "YES", then this course if for YOU!This course will expose you to a lot of Digital VLSI logic, design and architectural problems. This course will not only prepare you but also enhance your thought process when it comes to applying your knowledge to solve real world problems in the ASIC/ Digital Design world. Lot of System Verilog coding techniques which will help you understand how to use parameters and write RTL for scalability and reconfigurability which will help students differentiate themselves from competing candidates.The questions in this course will cover Microarchitecture, Design techniques, RTL coding, Power gating, Synthesis, UPF Flow, DFT, ECOs while keeping scaling and modular design in mind. It takes years in the industry to develop these design techniques and mindset.Lastly, the course will continue to evolve on a weekly basis. New lectures with latest questions and solutions will be added every week to help you keep up with the questions at the Big Tech companies.

Overview

Section 1: Introduction

Lecture 1 Introduction

Lecture 2 How The Course Will Evolve

Section 2: ASIC Design Concepts

Lecture 3 Async Vs. Sync Resets

Lecture 4 Do Async Resets Need Synchronization To Local Clk

Lecture 5 What Is The Difference Between AHB & AXI

Lecture 6 What Happens If Blocking Assignments Are Used For Sequential Logic

Lecture 7 How To Choose Between "Case" And "If-else" Statements

Section 3: Logic Design Questions

Lecture 8 Design INV, AND & OR Gate Using 2:1 Mux

Lecture 9 Convert A D-FF Into A Toggle Flip Flop

Lecture 10 Design A Ckt To Delay The Falling Edge Of The Pulse By 2 Clock Cycles

Lecture 11 Design A "Transitions" Circuit

Lecture 12 Design A Leading '1' Detector Ckt For 8-bit Input Bus

Lecture 13 Design A Divide-by-3 Clk

Lecture 14 Design A Divide-by-3 Clk With 50% Duty Cycle

Lecture 15 Implement A 8-Bit Skip-By-3 Counter

Lecture 16 Design A Divide-by-2/3 Clk Circuit

Lecture 17 How To Fix Timing Violation Caused By A Very Late Signal

Lecture 18 Calculate The FIFO Depth (Burst Size Case)

Lecture 19 Calculate The FIFO Depth

Lecture 20 Design A MinMax4 With MinMax2 Components

Lecture 21 Design A MinMax6 Circuit (Bonus Question)

Lecture 22 Design A Circuit With Minimum Logic

Lecture 23 How Will You Exchange The Contents Of "X" And "Y"

Lecture 24 Binary Or Gray: Which N-bit Counter Consumes More Power

Lecture 25 Design A Ckt To Count The Number of 1's In A 7-bit Vector

Lecture 26 Design A Ckt To Count The Number of 1's In A Bus

Lecture 27 Design A Random Delay Circuit Detector

Lecture 28 How Many Pattern Are Required To Detect A Wiring Mismatch

Lecture 29 Implement A Fibonacci Sequence In System Verilog

Lecture 30 Design A Ckt To Count Rising Edges

Lecture 31 Design A Circuit To Count Rising And Falling Edges

Lecture 32 Design A Ckt To Detect Pattern 10110

Lecture 33 Clock Domain Crossing Implementation Gotcha-1

Lecture 34 How To Add A Soft Reset To DFF

This course is for students who want to thoroughly prepare for upcoming ASIC/Digital Design interviews at Tech companies and ACE these interviews!!!

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